FPGA on William's Notes

FreePBX Syslog Setup

Sat, 10 Aug 2019 04:53:01 +0000

How to setup FreePBX to log to a syslog server. In my case I am using graylog with a syslog UDP input at port 1514.

Modify /etc/asterisk/logger_logfiles_custom.conf to add the desired items to be logged:

syslog.local0 => notice,warning,error,security

Modify /etc/rsyslog.conf and add the following line, matching the above destination:

local0.*                                  /var/log/asterisk/syslog

To forward to graylog I also uncommented the following in rsyslog.conf:

# ### begin forwarding rule ###
# The statement between the begin ... end define a SINGLE forwarding
# rule. They belong together, do NOT split them. If you create multiple
# forwarding rules, duplicate the whole block!
# Remote Logging (we use TCP for reliable delivery)
#
# An on-disk queue is created for this action. If the remote host is
# down, messages are spooled to disk and sent when it is up again.
$ActionQueueFileName fwdRule1 # unique name prefix for spool files
$ActionQueueMaxDiskSpace 1g   # 1gb space limit (use as much as possible)
$ActionQueueSaveOnShutdown on # save messages to disk on shutdown
$ActionQueueType LinkedList   # run asynchronously
$ActionResumeRetryCount -1    # infinite retries if host is down
# remote host is: name/ip:port, e.g. 192.168.0.1:514, port optional
*.* @10.0.1.38:1514
# ### end of the forwarding rule ###

Finally restart the asterisk logger and rsyslog:

asterisk -rx "logger reload"
service rsyslog restart

The following resources were helpful in getting this setup:

http://www.asteriskdocs.org/en/3rd_Edition/asterisk-book-html-chunk/Monitoring_id264504.html

https://community.freepbx.org/t/is-it-possible-to-export-freepbx-logs-to-syslog/51676/4

VHDL VU Meter

Fri, 15 Mar 2013 05:16:18 +0000

This is a pseudo-VU meter written in VHDL. I did it for an afternoon project to see what I could do with VHDL quickly.

I take the line level audio output from my computer and run it through a Schottky diode ( half wave rectification ), and then straight into a serial ADC. The rest is done on the Xilinx Spartan 3E FPGA.

A true VU meter would translate the volume level of the output signal to a certain dB level. Mine just peak detects the output of the ADC and then scales the output until I get good dynamic range out of the LEDs available. The end result could use some refinement, but I was happy with the rough draft.

About Me

Mon, 01 Jan 0001 00:00:00 +0000

I graduated with a B.Sc. degree in Electrical Engineering from the University of California San Diego in 2012. While there I focused on semiconductor materials and devices; I had the opportunity to work in a clean room creating diodes, LEDs, and MOSFETs from silicon wafers. I also worked with analog and digital circuits, a selection of different microcontrollers, and both Xilinx and Altera FPGAs.

I worked as an Electral Engineer at Innoflight in San Diego from 2013 until 2019 building RF transceivers for small satellites. In 2019 I had the opportunity to move out to Bulder, CO to work at Blue Canyon Technologies as an RF Systems Engineer.